添加std_logic_vectors错误[英] Error adding std_logic_vectors

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问题描述

我想拥有一个简单的模块,可以添加两个std_logic_vectors.但是,使用代码时 下面使用 +运算符,它不合成.

library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity add_module is
        port(
  pr_in1   : in std_logic_vector(31 downto 0);
  pr_in2   : in std_logic_vector(31 downto 0);
  pr_out   : out std_logic_vector(31 downto 0)  
        );
end add_module;

architecture Behavior of add_module is

begin

    pr_out <= pr_in1 + pr_in2;

end architecture Behavior;

我从XST收到的错误消息

行17. +在这种情况下无法具有此类操作数.

我想念图书馆吗?如果可能的话,我不想将输入转换为自然数.

非常感谢

推荐答案

您如何希望编译器知道您的std_logic_vectors是签名还是未签名?在这两种情况下,ADDER实施不是相同的,因此您需要明确地告诉编译器您想要做什么; - )

注意:stackoverflow中的VHDL语法突出显示很糟糕.复制/粘贴此代码在您首选的VHDL编辑器中以更轻松地读取它.

library IEEE; 
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_arith.all; -- don't use this
use IEEE.numeric_std.all; -- use that, it's a better coding guideline

-- Also, never ever use IEEE.std_unsigned.all or IEEE.std_signed.all, these
-- are the worst libraries ever. They automatically cast all your vectors
-- to signed or unsigned. Talk about maintainability and strong typed language...

entity add_module is
  port(
    pr_in1   : in std_logic_vector(31 downto 0);
    pr_in2   : in std_logic_vector(31 downto 0);
    pr_out   : out std_logic_vector(31 downto 0)  
  );
end add_module;

architecture Behavior of add_module is
begin

  -- Here, you first need to cast your input vectors to signed or unsigned 
  -- (according to your needs). Then, you will be allowed to add them.
  -- The result will be a signed or unsigned vector, so you won't be able
  -- to assign it directly to your output vector. You first need to cast
  -- the result to std_logic_vector.

  -- This is the safest and best way to do a computation in VHDL.

  pr_out <= std_logic_vector(unsigned(pr_in1) + unsigned(pr_in2));

end architecture Behavior;

其他推荐答案

否使用std_logic_arith - 我关于这个(有一定长度:).

do 使用numeric_std-并在实体端口上使用正确的类型.如果您正在做算术,请使用数值类型(整数或(UN)签名向量,适当).他们会很好地合成.

std_logic_vector S有益于

  • 当您不关心数值(一组控制位,一些随机数据位)
  • 当您不知道输入的类型时(例如,可以根据控制标志在签名和无符号数字上运行的加法器).

其他推荐答案

@Aurelien的好建议使用numeric_std.

请记住,添加两个32位值可能会导致33位值并决定要如何处理溢出.

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问题描述

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize.

library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity add_module is
        port(
  pr_in1   : in std_logic_vector(31 downto 0);
  pr_in2   : in std_logic_vector(31 downto 0);
  pr_out   : out std_logic_vector(31 downto 0)  
        );
end add_module;

architecture Behavior of add_module is

begin

    pr_out <= pr_in1 + pr_in2;

end architecture Behavior;

The error message I get from XST

Line 17. + can not have such operands in this context.

Do I miss a library? If possible, I do not wanna convert the inputs into natural numbers.

Many thanks

推荐答案

How do you want the compiler to know if your std_logic_vectors are signed or unsigned ? Adder implementation is not the same in these two cases, so you need to explicitly tell the compiler what you want it to do ;-)

Note: VHDL syntax highlighting in StackOverflow is crappy. Copy/paste this code in your preferred VHDL editor to read it more easily.

library IEEE; 
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_arith.all; -- don't use this
use IEEE.numeric_std.all; -- use that, it's a better coding guideline

-- Also, never ever use IEEE.std_unsigned.all or IEEE.std_signed.all, these
-- are the worst libraries ever. They automatically cast all your vectors
-- to signed or unsigned. Talk about maintainability and strong typed language...

entity add_module is
  port(
    pr_in1   : in std_logic_vector(31 downto 0);
    pr_in2   : in std_logic_vector(31 downto 0);
    pr_out   : out std_logic_vector(31 downto 0)  
  );
end add_module;

architecture Behavior of add_module is
begin

  -- Here, you first need to cast your input vectors to signed or unsigned 
  -- (according to your needs). Then, you will be allowed to add them.
  -- The result will be a signed or unsigned vector, so you won't be able
  -- to assign it directly to your output vector. You first need to cast
  -- the result to std_logic_vector.

  -- This is the safest and best way to do a computation in VHDL.

  pr_out <= std_logic_vector(unsigned(pr_in1) + unsigned(pr_in2));

end architecture Behavior;

其他推荐答案

Don't use std_logic_arith - I've written about this (at some length :).

Do use numeric_std - and do use the right type on your entity ports. If you are doing arithmetic, use numerical types (either integers, or (un)signed vectors, as appropriate). They'll synthesise perfectly well.

std_logic_vectors are good for

  • when you don't care about numerical values (a set of control bits, some random data bits)
  • when you don't know about the type of the input (say an adder which can operate on both signed and unsigned numbers based on a control flag).

其他推荐答案

Good advice from @Aurelien to use numeric_std.

Bear in mind that adding two 32 bit values can result in a 33 bit value and decide how you want to handle the overflow.