什么时候使用VHDL库std_logic_unsigned和numeric_std?[英] When to use VHDL library std_logic_unsigned and numeric_std?

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问题描述

i在ISE中使用VHDL-200X.我始终使用std_logic_vector,std_logic,integer,boolean和real和real的数据类型.总是使用std_logic_vector转换为integer和反向. 我的队友要求我使用library IEEE的这三个部分.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

但有人说不要使用IEEE.STD_LOGIC_UNSIGNED.ALL而不是IEEE.NUMERIC_STD.ALL. 在这里

我对此感到困惑,任何人都可以提供帮助?

推荐答案

切勿使用std_logic_arith或std_logic_**signed.始终使用numeric_std签名或需要无符号值.以前的包裹声称是IEEE,但不是.它们是摘要或导师图形的供应商特定扩展.

基于导入的软件包,std_logic_vector上均定义了算术操作.这个表示您不能在同一体系结构中使用签名和未签名值.

在integer中进行所有数学有一些缺点:

  • 没有非初始化的价值
  • 否'x'繁殖
  • 限制为32位
    (如何编写64位计数器?)

其他推荐答案

我的纯粹一方同意@pabbles. Otoh,我的务实的侧面异议.我的务实一方获胜,因此,我建议以下(直到支持Numeric_std_unsigned):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

对于RTL设计,我建议您使用签名和未签名的类型,适用于您认为是数学的所有操作.这是我的纯粹一面.

在RTL中,我永远不建议在std_logic_vector中进行数学,而是STD_LOGIC_UNSIGNED只是为了安全网.考虑所有关系运算符都是隐式定义的(=,/=,<,<=,>,> - ).在设计中,我们对值进行了很多比较:

if A = "00001" then 
. . . 
if B = X"1A" then 

如果A不是5位会发生什么?如果B不是8位会发生什么?如果您使用隐式定义的比较,则是错误的.如果使用std_logic_unsigned的比较,则可以使用尺寸不同.如果您不使用std_logic_unsigned,则您的测试台应该找到此问题.

因为" ="可以与RTL一起使用,如果有人在做地址解码器并写入:

Sel <= '1' when Addr > X"3FFF" else '0' ; 

如果a是16位,则可以解决.如果A不是16位怎么办?然后进行词典学(词典有序)比较. IE:" 100">" 01111"是正确的.

使用std_logic_unsigned,这些将通过无符号的数学规则来处理.在大多数情况下,这是正确的.如果没有STD_LOGIC_UNSIGN,这些将导致错误.如果您不使用std_logic_unsigned,并且对测试台感到谨慎,则应该找到此问题.

我担心的是,如果您不使用std_logic_unsigned,那么您的模拟电路与您合成的电路有所不同(因为合成工具倾向于创建与std_logic_unsigned一致的实现) .如果您错过了在模拟中捕捉到的,那么在评论中很难找到.因此,我建议使用普通关系操作员时std_logic_unsign作为安全网.

请注意,VHDL-2008引入了包装numeric_std_unsigned,我计划在所有合成工具中工作时切换到它.

我非常严格的一面说,我们应该通过创建其他软件包来解决订购操作(<,<=,>,> =)的问题由于歧义.注意我们不能以同样的方式保护" =".

VHDL-2008添加了匹配的关系操作"?=","?/=","?>",...当您的合成工具中可用时,我建议切换到这些.匹配的平等操作(?=,?/=)要求操作数为相同的长度 - 如果它们不相等,则意味着编译错误.匹配订购操作(?>,?> =,?<,?<=)仅在数学软件包中定义,例如numeric_std或numeric_std_unsigned - 因此,除非您使用适当的数学包,否则不能使用它们.

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问题描述

I use VHDL-200X in ISE.I always use data type like std_logic_vector,std_logic,integer,boolean and real.Always use std_logic_vector convert to integer and reverse. My team mates ask me to use these three parts of library IEEE.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

But someone said do not use IEEE.STD_LOGIC_UNSIGNED.ALL instead of IEEE.NUMERIC_STD.ALL.Because you have everything you need in numeric_std, and STD_LOGIC_UNSIGNED is not standard library. Here.

I confused about it and anybody can help?

推荐答案

Never use std_logic_arith or std_logic_**signed. Always use numeric_std when signed or unsigned values are needed. The former packages claim to be IEEE, but they aren't. They are vendor specific extensions from Synopsys or Mentor Graphics.

Both defined arithmetic operations on std_logic_vector based on the imported packages. This e.g. means you can't used signed and unsigned values in the same architecture.

Doing all math in integers has some drawbacks:

  • no uninitialized value
  • no 'X' propagation
  • limited to 32 bits
    (How to write a 64 bit counter?)

其他推荐答案

My purist side agrees with @Pabbles. OTOH, my pragmatic side dissents. My pragmatic side wins, and hence, I recommend the following (until numeric_std_unsigned is supported):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

For RTL design, I recommend that you use types signed and unsigned for all operations you consider to be math. This is my purist side.

In RTL, I never recommend doing math in std_logic_vector, instead, std_logic_unsigned is just there for a safety net. Consider that all relational operators are implicitly defined (=, /=, <, <=, >, >-). In a design, we do a lot of comparisons to values:

if A = "00001" then 
. . . 
if B = X"1A" then 

What happens if A is not 5 bits? What happens if B is not 8 bits? If you use the implicitly defined comparison, it is FALSE. If you use the comparison from std_logic_unsigned, it is ok if the sizes are different. If you are not using std_logic_unsigned, your testbench should find this issue.

Since "=" is ok to use with RTL, what if someone is doing an address decoder and writes:

Sel <= '1' when Addr > X"3FFF" else '0' ; 

If A is 16 bits, then it should work out ok. What if A is not 16 bits? Then it does a lexicographic (dictionary ordered) comparison. IE: "100" > "01111" is TRUE.

With std_logic_unsigned, these will be handled by unsigned math rules. Which for most cases is correct. Without std_logic_unsigned, these will result in FALSE. If you are not using std_logic_unsigned and you are careful with your testbenches, you should find this.

My concern is that if you don't use std_logic_unsigned then you have a potential that the circuit that you simulate will be different than the circuit that you synthesize (as the synthesis tools tend to create an implementation that is consistent with std_logic_unsigned). If you miss catching this in simulation, it will be real difficult to find in a review. Hence, I recommend std_logic_unsigned as a safety net when using ordinary relational operators.

Note that VHDL-2008 introduces the package numeric_std_unsigned and I plan on switching to that when it works across all synthesis tools.

My really strict side says that we should address the issues with the ordering operations (<, <=, >, >=) by creating additional packages that also overload them for std_logic_vector, and hence, use of them results in an error due to ambiguity. Note we cannot protect "=" this same way.

VHDL-2008 adds matching relational operations "?=", "?/=", "?>", ... when these are available in your synthesis tools, I recommend switching to these. The matching equality operations (?=, ?/=) require operands to be the same length - meaning compile error if they are not equal length. The matching ordering operations (?>, ?>=, ?<, ?<=) are only defined in a math package such as numeric_std or numeric_std_unsigned - hence, you cannot use them unless you are using an appropriate math package.