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问题描述
我是VHDL编码的初学者.我正在尝试使用VHDL实现频率乘数.我已经实现了频率分隔线，但是频率乘数并不容易.请给出一个实施的想法.
推荐答案
用于在FPGA中实现，您必须使用专用的FPGA资源，例如 apect-locked loop "> epect-locked loop(pll)<(请参阅 antera 和 xilinx )或数字时钟经理(DCM)(请参阅 xilinx )乘以一个频率.
这些资源可以基于输入频率创建输出频率:
f_out = (N / M) * f_in
PLL和DCM资源是特定于设备的，通常是非常高级的资源，可以对相位，延迟等进行其他控制，因此请查看所使用的设备中的资源.
其他推荐答案
可以使用触发器分配时钟频率.但是，无法通过纯数字电路执行时钟乘法.如Morten所述，使用PLL单元(这是混合电路，因此未直接用VHDL实现). PLL是FPGA中的内置单元，因此您要做的就是实例化.
在V. Pedroni的"电路设计和vhdl仿真"附录G中进行了一个详细的示例.该书中还包括了几个完整的示例USIGN PLL用于数据序列化的时钟乘法.
问题描述
I am a beginner in VHDL coding. I am trying to implement frequency multiplier using VHDL. I have implemented frequency divider, but frequency multiplier is not that easy. Please give an idea for implementing that.
推荐答案
For implementation in a FPGA, you must use a dedicated FPGA resource like Phase-Locked Loop (PLL) (see Altera and Xilinx) or Digital Clock Managers (DCM) (see Xilinx) to multiply a frequency.
These resources can create an output frequency based on an input frequency like:
f_out = (N / M) * f_in
The PLL and DCM resources are device specific, and often very advanced resources, that allows additional control over phase, delay, etc., so take a look at the resources in the device you are using.
其他推荐答案
A clock frequency can be divided using flip-flops. However, clock multiplication cannot be performed by purely digital circuits. As mentioned by Morten, a PLL unit (which is a hybrid circuit, thus not directly implemented with VHDL) is used for that. PLLs are built-in units in FPGAs, so all that you have to do is to instantiate them.
A detailed example on how to do it is in Appendix G of "Circuit Design and Simulation with VHDL", by V. Pedroni. Several complete examples usign PLLs for clock multiplication in data serializers are also included in that book.
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