VHDL中的时间戳[英] Time stamp in VHDL

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问题描述

VHDL中是否有任何功能用于获取流程正在运行的当前仿真时间?可能与Systemc sc_time_stamp()

中的功能相同

推荐答案

是的.使用关键字now.

您可以使用VHDL属性打印模拟时间:

report "current time = " & time'image(now);

您还可以将当前时间存储到变量:

variable v_TIME : time := 0 ns;
v_TIME := now;
-- STUFF HAPPENS
v_TIME := now - V_TIME; --used to find delta time

其他推荐答案

如果您想知道合成设计中的时间,则必须自己管理.例如,可以使用与其余逻辑的同一时钟时钟进行的自由运行计数器,可用于将特定事件的时间捕获到寄存器中.然后,您可以将这些寄存器定期通过某个接口传输到主机PC或类似的PC,也可以使用嵌入式逻辑分析仪.

now是纯模拟构造,它告诉您模拟时间的模拟时间,该分辨率设置为任何分辨率.真正的硬件没有实时概念,只有时钟周期,也没有用于访问控制台的标准化界面,因此能够合成report time'image(now)甚至不是遥不可及的选择.

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问题描述

is there any function in VHDL which is used to get current simulation time at which a process is running? May be same like the function in systemC sc_time_stamp()

推荐答案

Yes there is. Use the keyword now.

You can print the simulation time using VHDL Attributes:

report "current time = " & time'image(now);

You can also store the current time to a variable:

variable v_TIME : time := 0 ns;
v_TIME := now;
-- STUFF HAPPENS
v_TIME := now - V_TIME; --used to find delta time

其他推荐答案

If you want to know the time within your synthesised design, you will have to manage that yourself. For example, a free-running counter clocked from the same clock as the rest of your logic can be used to capture the time of particular events into registers. You could then transfer those registers periodically over some interface to a host PC or similar, or use an embedded logic analyser.

now is a purely simulation only construct, which tells you the simulation time to whatever resolution the simulator is set to. The real hardware has no concept of real time, only clock cycles, and has no standardised interface for accessing a console, so being able to synthesise report time'image(now) is not even remotely an option.