使用VHDL代码生成一个纯正弦波作为FPGA的输出形式[英] Generating a pure sine wave as output form FPGA using VHDL code

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问题描述

我们知道,FPGA的输出是数字的,但是我们可以使用VHDL代码纯化纯模拟正弦波.我也可以指定正弦波的频率.

推荐答案

定义"纯" - 您可以使用多少"定量" ...以及什么频率?

对于低位的低频率,您可以在FPGA中构建一个简单的PWM或Delta-Sigma DAC,并在"外部"上放置一个低通滤波器(对不起,这必须是真正的模拟硬件:). 此示例可能是有益的

没有某种外部组件就不会到达那里.

其他推荐答案

您可以查看直接数字合成.它基本上使用ROM存储正弦样品,并使用相位蓄能器将其索引到ROM中,以以所需的频率生成输出信号.分辨率和最大频率受FPGA时钟和ROM大小的约束.

不过,您仍然需要一个ANLOG重建过滤器.

其他推荐答案

从先前存储的样品中生成纯正弦波的方法,并在不同的速率/内存位置读取存储器以更改正弦波的频率和/或光谱纯度称为直接数字合成.

这使您可以使用所需的光谱纯度生成广泛的正弦频率.在手机和软件定义的无线电和任何其他类似应用程序中都有用. DDS ASIC也可用,但通常很昂贵.

FPGA是更便宜的选择. FPGA只能生成所需的数字输出,但是在没有过滤器或DAC和一些基本过滤的情况下,不能生成模拟单声道.

大多数FPGA供应商都具有其IDE(集成开发环境)的免费DDS IP核心.结帐Actel/Xilinx/Altera IP.他们有空.如果您无法设法获得IP,则可以在MATLAB中拉出DDS功能块,并利用第三方工具.(可在上面的所有三个供应商中使用)以通过MATLAB接口合成DDS. DDS有时也称为DDF:直接数字频率合成.

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问题描述

We know that the output of an FPGA is digital but can we genrate a pure analog sine wave using a vhdl code. also can I specify the frequency of the sine wav.

推荐答案

Define "pure" - how many "bits" of quantisation can you live with... and what frequency?

For lowish frequencies at lowish bits you could build a simple PWM or delta-sigma DAC in the FPGA and put a low-pass filter on the "outside" (sorry, that'll have to be real analogue hardware :) . This example may be informative

Not going to get there without some external componentry though.

其他推荐答案

You can look into Direct Digital Synthesis. It basically uses a ROM to store the sine samples and uses a phase accumulator to index into the ROM to generate the output signal with the desired frequency. Resolution and maximum frequency is bound by the fpga clock and the ROM size.

You still need an anlog reconstruction filter, though.

其他推荐答案

The Method of generating Pure Sine waves from a previously stored samples in memory & reading the memory at varying rate / memory locations to change the frequency and or the spectral purity of the sine wave is called Direct Digital Synthesis.

This allows you to generate wide range of sine freq's with the required spectral purity. Useful in Mobiles & Software Defined Radio's & any other similar application. DDS ASIC's are also available but are usually expensive.

FPGA's are cheaper alternative. FPGA can only generate the required Digital output , but the analog singal cant be generated without a filter or a DAC & some basic filtering.

Most FPGA vendors have a free DDS IP Core with their IDE (Integrated Dev Environment). Checkout Actel/ Xilinx / Altera IP's. They're free. If you cannot manage to get an IP, you can pull a DDS function block in Matlab & utilize a 3rd party tool .. (available with all three above vendors) to synthesize a DDS via Matlab Interface . DDS is sometimes also known as DDFS : Direct Digital Frequency Synthesis.