# 如何在VHDL中做矢量乘积[英] How to do a vector product in VHDL

### 问题描述

```type array_4_8bit is array (0 to 3) of std_logic_vector(7 downto 0);
signal Array_Last4Vals : array_4_8bit;
signal Multiplier : array_4_8bit;
Array_Last4Vals <= [5, 6, 7, 8]; -- will replace these numbers with the corresponding binary numbers
Multiplier <= [1, 2, 3, 4]; -- will replace these numbers with the corresponding binary numbers
product <= Multiplier*Array_Last4Vals;
```

i然后希望该产品在此示例中为[5、12、21、32].

## 推荐答案

vhdl允许为自定义类型重新定义infix运算符(例如*)，因此您可以声明执行矢量乘法的函数，例如:

```function "*"(a, b : array_4_8bit) return array_4_8bit is
variable result_v : array_4_8bit;
begin
for idx in result_v'range loop
result_v(idx) := std_logic_vector(unsigned(a(idx)) * unsigned(b(idx)));
end loop;
return result_v;
end function;
```

```type array_4_integer is array (0 to 3) of integer;

function to_array_4_8bit(v : array_4_integer) return array_4_8bit is
variable result_v : array_4_8bit;
begin
for idx in result_v'range loop
result_v(idx) := std_logic_vector(to_unsigned(v(idx), 8));
end loop;
return result_v;
end function;

Array_Last4Vals <= to_array_4_8bit((5, 6, 7, 8));
Multiplier <= to_array_4_8bit((1, 2, 3, 4));
```

### 问题描述

How would I go about doing a vector product in VHDL?

e.g. I have 2 vectors defined like so:

```type array_4_8bit is array (0 to 3) of std_logic_vector(7 downto 0);
signal Array_Last4Vals : array_4_8bit;
signal Multiplier : array_4_8bit;
Array_Last4Vals <= [5, 6, 7, 8]; -- will replace these numbers with the corresponding binary numbers
Multiplier <= [1, 2, 3, 4]; -- will replace these numbers with the corresponding binary numbers
product <= Multiplier*Array_Last4Vals;
```

I then want the product to be [5, 12, 21, 32] in this example.

How would I go about doing that?

## 推荐答案

VHDL allows re-definition of infix operators, like *, for custom types, so you can declare a function that does the vector multiplication like:

```function "*"(a, b : array_4_8bit) return array_4_8bit is
variable result_v : array_4_8bit;
begin
for idx in result_v'range loop
result_v(idx) := std_logic_vector(unsigned(a(idx)) * unsigned(b(idx)));
end loop;
return result_v;
end function;
```

Assumption above is that he vector elements are unsigned values, and that the result of each multiplication is truncated to 8 bits.

For generation of the input data, you can also consider doing:

```type array_4_integer is array (0 to 3) of integer;

function to_array_4_8bit(v : array_4_integer) return array_4_8bit is
variable result_v : array_4_8bit;
begin
for idx in result_v'range loop
result_v(idx) := std_logic_vector(to_unsigned(v(idx), 8));
end loop;
return result_v;
end function;

Array_Last4Vals <= to_array_4_8bit((5, 6, 7, 8));
Multiplier <= to_array_4_8bit((1, 2, 3, 4));
```