如何在verilog中使用Counter for Synthesis生成延迟，并在Always块内调用？[英] How to generate delay in verilog using Counter for Synthesis and call inside Always block?

问题描述

I want to generate delay using counter, actually here I use counter to generate delay after each 1 Bit transfer, so that its better understand externally on fpga pin from which by SPI(serial) LCD is connected with it. Therefore I had created a shift register which shift 1 bit then gives delay then next bit(Bit-Delay-bit-delay..).

Here is my code of counter:

module spidelay(
  input  wire clk,
  input  wire enb,
  output reg  sclkout
);
  reg [23:0] stmp;

  always @(posedge clk) begin
    if ( enb == 1 ) begin
      stmp = stmp+1;
      if( stmp[23] == 1 ) begin
        sclkout = 1'b1;
        stmp    = 24'b0;
       end
    end
    else begin
      stmp    = 24'b0;
      sclkout = 1'b0;
   end
 end
endmodule

Friends but problem with it is I don't know how to enable/start counter inside always block I mean I don't know how can we start /enable counter at line which we want to generate delay inside always.

Now this is the code of my Top module from which I want to generate delay in particular line--->>

 module Nokia_LCD(input clk,input switch,output OUT,output reset,inout sck,output cs);  
     wire clk;//On Board Clock
     wire switch;//Switch For RESET
     integer i;
     integer z;//Used for, for loop for generating delay
     reg signed OUT;//OUT for sending Data serially to LCD
     reg reset=1'b1;//To Reset LCD
     wire sck; //We select sck as inout because it taking input from counter Instance and then gives output to LCD..
     reg cs; //Chip select pin of lcd always set to zero 
     reg signed[8:0]out;//Register for Storing value of OUT
     reg [5:0]state =6'b000000; //Initialize states to Zero
     reg [7:0]finder; //Finder finds the state that was last present in it so that by this we again go to that state sequentially 
     reg [7:0]font[1:0][5:0];//2-D Array of 8 Bit For Font 
     reg [23:0]stmp=24'b00000_00000_00000_00000_0000;
     reg enb;
     wire sclkout;

     counter count1(clk,sck);//Instance of Counter1 for SCK Clock
     spidelay count2(clk,enb,sclkout);

    always@(posedge clk)
    begin
    case (state)

      /* Lcd Initialization starts from here*/
           6'b000000 : begin
           finder=8'b00000000;
           cs=1'b0;
             out=9'b0_00010001; //Using Command SLEEPOUT (Hex 0x11) - Exits LCD sleep mode
             state=6'b010001; 
           end

           6'b000001: begin
           finder=8'b00000001;
           cs=1'b0; 
             out=9'b0_00000011; //Using Command BSTRON (Hex 0x03) - Turns on booster voltage     
             state =6'b010001; 
             end 

      /******************************************************************************************************************/
      /************************************ State for SPI Data Transfer & Delay *****************************************/
      /******************************************************************************************************************/ 
           6'b010001:begin

           //We Use finder to find the state from which it Comes...

             if(finder==8'b00000000) //for 0
                     begin:close1         
                     cs=1'b0;
            for(i=0;i<=8;i=i+1)
            begin
            out=out<<<1;
            OUT=out[8];
              enb=1'b1;  <<<<<<<-----|This is the place where I want it to enable counter and it must stop here  for counting and during this time it not move for othe count of for loop......


            if(stmp[23]==1'b1)
             begin
             disable close1;
             end
             end
             state=6'b000001;//Go to State 000001(BSTRON)
         end    




       endcase  

     end //Always end


    endmodule

It must be noted that Friends I am edited it so that to concentrate on the point of of error....so if somewhere you find error in syntax then ignore it but please help me and give some suggestion to generate delay on Toppest Module's always block by giving enb=1'b1 .......

推荐答案

It is recommended to use <= inside edge triggered blocks always @( posedge ...

You mention delays I assume you are referring to delaying by a fixed number of clock cycles. In which case this is what you have done, you just have not reset the sclkout when not meeting the counter requirements.

if ( enb == 1 ) begin
  sclkout <= 1'b0;  //Reset by default
  stmp    <= stmp+1;

  if( stmp[23] == 1 ) begin //Counter target
    sclkout <= 1'b1;
    stmp    <= 24'b0;
  end
end
else begin
  //...

Or add in an else

if ( enb == 1 ) begin
  if( stmp[23] == 1 ) begin //Counter target
    sclkout <= 1'b1;
    stmp    <= 24'b0;
  end
  else begin
    sclkout <= 1'b0;  //Reset by default
    stmp    <= stmp+1;
  end
end
else begin
  //...

NB: inputs are implicitly wires you do not have to write it if you do not want to. input wire clk is the same as input clk.

I would also add a width to your comparisons, ie == 1'b0 instead of == 0, otherwise later on in you design flow you will get width mismatch warnings.

Update
Based on information add in the comment, the requirment is for the counter to stop when enb==1'b1, I am assuming that stands for 'enable bar'

always @ (posedge clk) begin
  if ( enb == 1'b0 ) begin
   // When enable bar is low this is Active
   stmp    <= stmp + 1'b1;
   // etc ...
  end
  //else begin
  //  Do Nothing (hold state)
  //end
end