如何用chisel生成一个异步复位的verilog总是块[英] How to generate an asynchronous reset verilog always blocks with chisel

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问题描述

凿子生成总是在感应性列表中只有时钟的封锁:

always @posedge(clk) begin
  [...]
end

是否可以配置模块使用异步重置并生成总是这样的块?

always @(posedge clk or posedge reset) begin
   [...]
end

推荐答案

由于凿子3.2.0,因此支持同步,异步和抽象重置类型.根据明确指定或推断的重置类型,您将获得规范同步或异步Verilog输出.

要更充分地显示此内容,请考虑以下MultiIOModule具有三个重置:

  • 隐式reset具有抽象重置类型的输入(这是"抽象重置")
  • 具有Bool类型的显式syncReset输入(这是"同步重置")
  • 具有AsyncReset类型的显式asyncReset输入(这是"异步重置")

使用withReset,可以在设计中的不同寄存器中使用特定的重置连接:

import chisel3._
import chisel3.stage.ChiselStage

class Foo extends MultiIOModule {
  val syncReset  = IO(Input(Bool()      ))
  val asyncReset = IO(Input(AsyncReset()))

  val in          = IO(Input( Bool()))
  val outAbstract = IO(Output(Bool()))
  val outSync     = IO(Output(Bool()))
  val outAsync    = IO(Output(Bool()))

  val regAbstract =                         RegNext(in, init=0.U)
  val regSync     = withReset(syncReset)  { RegNext(in, init=0.U) }
  val regAsync    = withReset(asyncReset) { RegNext(in, init=0.U) }

  outAbstract := regAbstract
  outSync     := regSync
  outAsync    := regAsync
}

然后,当与:(new ChiselStage).emitVerilog(new Foo):

编译时,这将产生以下verilog
module Foo(
  input   clock,
  input   reset,
  input   syncReset,
  input   asyncReset,
  input   in,
  output  outAbstract,
  output  outSync,
  output  outAsync
);
  reg  regAbstract;
  reg  regSync;
  reg  regAsync;
  assign outAbstract = regAbstract;
  assign outSync = regSync;
  assign outAsync = regAsync;
  always @(posedge clock) begin
    if (reset) begin
      regAbstract <= 1'h0;
    end else begin
      regAbstract <= in;
    end
    if (syncReset) begin
      regSync <= 1'h0;
    end else begin
      regSync <= in;
    end
  end
  always @(posedge clock or posedge asyncReset) begin
    if (asyncReset) begin
      regAsync <= 1'h0;
    end else begin
      regAsync <= in;
    end
  end
endmodule

注意:在凿子3.2中,顶级抽象重置将始终设置为同步重置.在凿子3.3.0中,添加了两个特征:RequireSyncReset和RequireAsyncReset.这些可用于将连接到regAbstract的寄存器的重置类型从同步到异步.用(new ChiselStage).emitVerilog(new Foo with RequireAsyncReset)重新编译设计,将(new ChiselStage).emitVerilog(new Foo with RequireAsyncReset)逻辑更改为

always @(posedge clock or posedge reset) begin
  if (reset) begin
    regAbstract <= 1'h0;
  end else begin
    regAbstract <= in;
  end
end

有关更多信息, Chisel网站有更多有关RESETSETS的信息.

其他推荐答案

3.2.0之前的凿子版本不支持异步重置.

看起来在凿子中这样做的方法是使用同步重置:

always @posedge(clk) begin
  if (reset) begin
  [...]
  end 
  else 
  [...]
  end
end

有关该主题的更多讨论: https://groups.google.com/forum/# !!凿子 - 用户/4cc4syb5mk8

本文地址:https://www.itbaoku.cn/post/2090996.html

问题描述

Chisel generate always blocks with only clock in sensivity list :

always @posedge(clk) begin
  [...]
end

Is it possible to configure Module to use an asynchronous reset and generate an always block like this ?

always @(posedge clk or posedge reset) begin
   [...]
end

推荐答案

Since Chisel 3.2.0, there is support for synchronous, asynchronous, and abstract reset types. Based on the type of reset explicitly specified or inferred, you will get canonical synchronous or asynchronous Verilog output.

To try to show this more fully, consider the following MultiIOModule which has three resets:

  • The implicit reset input which has an abstract reset type (this is "abstract reset")
  • The explicit syncReset input which has a Bool type (this is "synchronous reset")
  • The explicit asyncReset input which has an AsyncReset type (this is "asynchronous reset")

Using withReset, specific reset connections can then be used for different registers in the design:

import chisel3._
import chisel3.stage.ChiselStage

class Foo extends MultiIOModule {
  val syncReset  = IO(Input(Bool()      ))
  val asyncReset = IO(Input(AsyncReset()))

  val in          = IO(Input( Bool()))
  val outAbstract = IO(Output(Bool()))
  val outSync     = IO(Output(Bool()))
  val outAsync    = IO(Output(Bool()))

  val regAbstract =                         RegNext(in, init=0.U)
  val regSync     = withReset(syncReset)  { RegNext(in, init=0.U) }
  val regAsync    = withReset(asyncReset) { RegNext(in, init=0.U) }

  outAbstract := regAbstract
  outSync     := regSync
  outAsync    := regAsync
}

This then produces the following Verilog when compiled with: (new ChiselStage).emitVerilog(new Foo):

module Foo(
  input   clock,
  input   reset,
  input   syncReset,
  input   asyncReset,
  input   in,
  output  outAbstract,
  output  outSync,
  output  outAsync
);
  reg  regAbstract;
  reg  regSync;
  reg  regAsync;
  assign outAbstract = regAbstract;
  assign outSync = regSync;
  assign outAsync = regAsync;
  always @(posedge clock) begin
    if (reset) begin
      regAbstract <= 1'h0;
    end else begin
      regAbstract <= in;
    end
    if (syncReset) begin
      regSync <= 1'h0;
    end else begin
      regSync <= in;
    end
  end
  always @(posedge clock or posedge asyncReset) begin
    if (asyncReset) begin
      regAsync <= 1'h0;
    end else begin
      regAsync <= in;
    end
  end
endmodule

Note: that in Chisel 3.2 the top-level abstract reset would always be set to synchronous reset. In Chisel 3.3.0, two traits were added: RequireSyncReset and RequireAsyncReset. These can be used to change the reset type of the register connected to regAbstract from synchronous to asynchronous. Recompiling the design with (new ChiselStage).emitVerilog(new Foo with RequireAsyncReset), changes the regAbstract logic to

always @(posedge clock or posedge reset) begin
  if (reset) begin
    regAbstract <= 1'h0;
  end else begin
    regAbstract <= in;
  end
end

For more information, the Chisel website has more information on resets.

其他推荐答案

Chisel versions prior to 3.2.0 do not have support for asynchronous resets.

It looks like the way to do this in Chisel is to use synchronous resets:

always @posedge(clk) begin
  if (reset) begin
  [...]
  end 
  else 
  [...]
  end
end

For more discussion on the topic: https://groups.google.com/forum/#!topic/chisel-users/4cc4SyB5mk8