信号电流无法合成,同步描述不好[英] Signal current cannot be synthesized, bad synchronous description

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问题描述

我在xillinx中合成此代码时有错误.此错误是:

在库中分析实体(架构).
错误:XST:827-" C:/Xilinx92i/parking/parking.vhd"行43:信号电流无法合成,不良同步描述.

entity Parking is port(
    A, B ,reset: in std_logic;
    Capacity : out std_logic_vector(7 downto 0));
end Parking;

architecture Behavioral of Parking is
    type state is (NoChange, Aseen, Bseen, ABseen, BAseen, Input, Output, Din, Dout);
    signal current, nxt : state ;
    signal counter : std_logic_vector (7 downto 0) := "00000000";
begin

    p1: process(A, B, reset)
    begin
        if reset = '1' then
            current <= Nochange;
        end if;

        if(A'event and A='1') then
            current <= nxt;
        end if;

        if(A'event and A='0') then
            current <= nxt;
        end if;

        if(B'event and B='1') then
            current <= nxt;
        end if;

        if(B'event and B='0') then
            current <= nxt;
        end if;
    end process;

    p2: process(current, A, B)
    begin
        case current is
            when Aseen =>
                if B='1' then
                    nxt <= ABseen;
                else
                    nxt <= NoChange;
                end if;

            when others =>
                nxt <= Nochange;
        end case;
    end process;

    Capacity <= counter;

end Behavioral;

推荐答案

错误'错误同步描述'通常意味着您已经描述了硬件中不存在的寄存器(时钟元素).

在您的代码中,您有:

if(A'event and A='1') then
   current <= nxt;
end if;

if(A'event and A='0') then
    current <= nxt;
end if;

-- etc

在一个过程中.同步合成过程通常只有一个时钟,因为像FPGA这样的真实硅设备中没有元素可以在两个不同时钟上响应事件.像您要实现的过程一样,通常看起来更像是这样的东西:

process (clk)   
begin
    if (rising_edge(clk)) then
        if (a = '1') then
            current <= nxt;
        elsif (a = '0') then
            current <= nxt;
        end if;
    end if;
end process;

以这种方式实施它需要您:

  1. 您系统中的时钟
  2. 相对于此时钟相对于设置/保持时间输入

侧注

如果您没有一个有意义的流程名称,则根本不必给它一个. process (clk)与p1 : process(clk).

一样有效

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问题描述

I have a error while Synthesize this code in Xillinx. This error is:

Analyzing Entity in library (Architecture ).
ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description.

entity Parking is port(
    A, B ,reset: in std_logic;
    Capacity : out std_logic_vector(7 downto 0));
end Parking;

architecture Behavioral of Parking is
    type state is (NoChange, Aseen, Bseen, ABseen, BAseen, Input, Output, Din, Dout);
    signal current, nxt : state ;
    signal counter : std_logic_vector (7 downto 0) := "00000000";
begin

    p1: process(A, B, reset)
    begin
        if reset = '1' then
            current <= Nochange;
        end if;

        if(A'event and A='1') then
            current <= nxt;
        end if;

        if(A'event and A='0') then
            current <= nxt;
        end if;

        if(B'event and B='1') then
            current <= nxt;
        end if;

        if(B'event and B='0') then
            current <= nxt;
        end if;
    end process;

    p2: process(current, A, B)
    begin
        case current is
            when Aseen =>
                if B='1' then
                    nxt <= ABseen;
                else
                    nxt <= NoChange;
                end if;

            when others =>
                nxt <= Nochange;
        end case;
    end process;

    Capacity <= counter;

end Behavioral;

推荐答案

The error 'bad synchronous description' usually means that you have described a register (clocked element) that does not exist in the hardware.

In the case of your code, you have:

if(A'event and A='1') then
   current <= nxt;
end if;

if(A'event and A='0') then
    current <= nxt;
end if;

-- etc

inside one process. Synchronous synthesisable processes will typically only have one clock, because there is no element in a real silicon device like an FPGA that can respond to events on two different clocks. A process like the one you are trying to implement would typically look something more like this:

process (clk)   
begin
    if (rising_edge(clk)) then
        if (a = '1') then
            current <= nxt;
        elsif (a = '0') then
            current <= nxt;
        end if;
    end if;
end process;

Implementing it this way requires that you have:

  1. A clock in your system
  2. Inputs that meet setup/hold times relative to this clock

Side note

If you don't have a meaningful name for a process, you don't have to give it one at all. process (clk) is just as valid as p1 : process(clk).