GHDL仿真器不支持vhdl属性,没有错误?[英] GHDL simulator doesn't support vhdl attributes without error?

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问题描述

我编写了一些Vivado RTL,然后在实体的端口中添加了一些VHDL属性,以将接口定义为Xilinx Vivado工具:

library ieee;
use     ieee.std_logic_1164.all;

entity vivado_rtl_island is

port(
    -- Clocks
    i_m50_clk                    :in   std_logic;
    i_m50_rst                    :in   std_logic;                                           

    -- APB Command Inteface
    s_paddr                  :in  std_logic_vector(31 downto 0);   
    s_psel                   :in  std_logic;                       
    s_penable                :in  std_logic;                       
    s_pwrite                 :in  std_logic;                       
    s_pwdata                 :in  std_logic_vector(31 downto 0);   
    s_pready                 :out std_logic;                       
    s_prdata                 :out std_logic_vector(31 downto 0);   
    s_pread                  :out std_logic;
    s_pslverr                :out std_logic
);

end entity;

architecture rtl of vivado_rtl_island is
  -- Define APB Interface for "Vivado IP Integrator"
  ATTRIBUTE X_INTERFACE_INFO:              STRING;
  ATTRIBUTE X_INTERFACE_INFO of s_paddr:   SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PADDR";
  ATTRIBUTE X_INTERFACE_INFO of s_psel:    SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSEL";
  ATTRIBUTE X_INTERFACE_INFO of s_penable: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PENABLE";
  ATTRIBUTE X_INTERFACE_INFO of s_pwrite:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWRITE";
  ATTRIBUTE X_INTERFACE_INFO of s_pwdata:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWDATA";
  ATTRIBUTE X_INTERFACE_INFO of s_pready:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PREADY";
  ATTRIBUTE X_INTERFACE_INFO of s_prdata:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PRDATA";
  ATTRIBUTE X_INTERFACE_INFO of s_pslverr: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSLVERR";
begin

 end architecture;

在那里,我尝试使用GHDL来编译上述RTL如下:

$ ghdl -a --std=08 --ieee=synopsys --work=work  vivado_rtl_island.vhd

GHDL产生以下错误:

vivado_rtl_island.vhd:28:33: no "s_paddr" for attribute specification
vivado_rtl_island.vhd:29:33: no "s_psel" for attribute specification
vivado_rtl_island.vhd:30:33: no "s_penable" for attribute specification
vivado_rtl_island.vhd:31:33: no "s_pwrite" for attribute specification
vivado_rtl_island.vhd:32:33: no "s_pwdata" for attribute specification
vivado_rtl_island.vhd:33:33: no "s_pready" for attribute specification
vivado_rtl_island.vhd:34:33: no "s_prdata" for attribute specification
vivado_rtl_island.vhd:35:33: no "s_pslverr" for attribute specification

但是,当我使用modelsim进行编译时,它不会产生错误.

有人知道如何在GHDL中解决此问题,以便我可以添加这些属性,并且模拟器会忽略它们并且不会产生和错误?

推荐答案

请参阅IEEE STD 1076-2008 7.2属性规范,第9段:

属性声明,体系结构,配置或软件包的属性规范应立即出现在该声明的声明部分中.同样,设计单元的接口对象的属性,子程序,块语句或软件包的属性规范应立即出现在该设计单元的声明部分,子程序,块语句或软件包.同样,设计单元,子程序,块语句或软件包的接口对象属性的属性规范应立即出现在该设计单元,子程序,块语句或软件包的声明部分中. ...

设计单元是实体声明(3.2实体声明),一个主要单元(13.1个设计单位).每个IEEE STD 1076修订版(-1987至-2008)在5.2属性规范中发现的-2008之前,这种语义限制已在ARRE限制(-1987至-2008)中. Modelsim是"编译"您的规格的错误.

xilinx的Vivado合成历史上利用了模型行为.这里有趣的是,Vivado不一致地遵守了上面的第一个引用句子的语义要求,这在早期的修订中也可以找到,但第二次也没有找到.您可以在实体声明部分中声明一个属性,而Vivado至少历史上必需的属性在架构声明部分中指定端口.

.

使用GHDL时不会丢失.有一个命令行参数可以在分析过程中传递,以放宽各种规则,以匹配模型的行为,而模型的行为依赖于第三方工具.

ghdl -a --std=08 --ieee=synopsys -frelaxed-rules --work=work vivado_rtl_island.vhdl
vivado_rtl_island.vhdl:28:33:warning: attribute for port "s_paddr" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:29:33:warning: attribute for port "s_psel" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:30:33:warning: attribute for port "s_penable" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:31:33:warning: attribute for port "s_pwrite" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:32:33:warning: attribute for port "s_pwdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:33:33:warning: attribute for port "s_pready" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:34:33:warning: attribute for port "s_prdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:35:33:warning: attribute for port "s_pslverr" must be specified in the entity [-Wspecs]

您可以添加命令行标志-frelaxed-rules,并且错误将转换为警告.

对于标准修订-2008,更改了默认的GHDL行为.您需要注意,如果不指定--std=08默认标准合规性为--std=93c,它包括-frelaxed-rules,否则与`-Std = 93(-1993)兼容.没有包含轻松规则的-2008修订.

语义限制背后的原因将源于领先(当时-1987)供应商无法实现在端口上指定用户属性的情况,而无需直接访问端口声明.尽管该供应商可能不再提供VHDL产品,但限制仍然存在.

我们发现,模型的各种实例有效地试图通过市场份额的影响来指导标准(它们具有命令行-pendanticerrors参数将很多警告更改为错误).

GHDL的开发遵循其领导,但严格遵守标准是指命令行参数的规范(--std=93c默认情况下)启用警告而不是错误.

.

这样做的原因是,那些实施VHDL的人倾向于从标准中做到这一点,而不是通过最大市场份额的供应商进行反向工程.

-Frelaxed -rules描述在ghdl 文档中可能无法完成. .在 vhdl标准以及其他部分.

xilinx已意识到这个问题. Modelsim无疑知道它们与标准的不同之处,目前没有供应商参与VHDL标准修订过程.

浏览GHDL源树GHDL-0.35于2017年12月14日发布,问题525 问题838 xilinx vivado and Modelsim and Modelsim在端口上的支持属性不同于GHDL的属性,在GitHub上,OP寻求第二个意见,说明此答案是有效的.

其他推荐答案

您正在使用VHDL2008,显然是.

使用VHDL 2008,实体端口属性必须进入实体定义,即您需要在end entity语句之前移动属性.

其他推荐答案

与GHDL这样的编译:

ghdl.exe -a -frelaxed-rules --std=08 --ieee=synopsys --work=work ./vivado_rtl_island.vhd

并将端口属性移至架构块... 然后,它将与Xilinx Vivado和GHDL保持一致.

本文地址:https://www.itbaoku.cn/post/2090998.html

问题描述

I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows:

library ieee;
use     ieee.std_logic_1164.all;

entity vivado_rtl_island is

port(
    -- Clocks
    i_m50_clk                    :in   std_logic;
    i_m50_rst                    :in   std_logic;                                           

    -- APB Command Inteface
    s_paddr                  :in  std_logic_vector(31 downto 0);   
    s_psel                   :in  std_logic;                       
    s_penable                :in  std_logic;                       
    s_pwrite                 :in  std_logic;                       
    s_pwdata                 :in  std_logic_vector(31 downto 0);   
    s_pready                 :out std_logic;                       
    s_prdata                 :out std_logic_vector(31 downto 0);   
    s_pread                  :out std_logic;
    s_pslverr                :out std_logic
);

end entity;

architecture rtl of vivado_rtl_island is
  -- Define APB Interface for "Vivado IP Integrator"
  ATTRIBUTE X_INTERFACE_INFO:              STRING;
  ATTRIBUTE X_INTERFACE_INFO of s_paddr:   SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PADDR";
  ATTRIBUTE X_INTERFACE_INFO of s_psel:    SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSEL";
  ATTRIBUTE X_INTERFACE_INFO of s_penable: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PENABLE";
  ATTRIBUTE X_INTERFACE_INFO of s_pwrite:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWRITE";
  ATTRIBUTE X_INTERFACE_INFO of s_pwdata:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWDATA";
  ATTRIBUTE X_INTERFACE_INFO of s_pready:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PREADY";
  ATTRIBUTE X_INTERFACE_INFO of s_prdata:  SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PRDATA";
  ATTRIBUTE X_INTERFACE_INFO of s_pslverr: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSLVERR";
begin

 end architecture;

There I try to compile the above rtl using GHDL as follows:

$ ghdl -a --std=08 --ieee=synopsys --work=work  vivado_rtl_island.vhd

GHDL produces the following error:

vivado_rtl_island.vhd:28:33: no "s_paddr" for attribute specification
vivado_rtl_island.vhd:29:33: no "s_psel" for attribute specification
vivado_rtl_island.vhd:30:33: no "s_penable" for attribute specification
vivado_rtl_island.vhd:31:33: no "s_pwrite" for attribute specification
vivado_rtl_island.vhd:32:33: no "s_pwdata" for attribute specification
vivado_rtl_island.vhd:33:33: no "s_pready" for attribute specification
vivado_rtl_island.vhd:34:33: no "s_prdata" for attribute specification
vivado_rtl_island.vhd:35:33: no "s_pslverr" for attribute specification

However, when I compile this with modelsim, it doesn't produce an error.

Does anybody know how to work around this problem in GHDL so that I can add these attributes and the simulator will ignore them and not produce and error?

推荐答案

See IEEE Std 1076-2008 7.2 Attribute specification, paragraph 9:

An attribute specification for an attribute of an entity declaration, an architecture, a configuration, or a package shall appear immediately within the declarative part of that declaration. Similarly, an attribute specification for an attribute of an interface object of a design unit, subprogram, block statement, or package shall appear immediately within the declarative part of that design unit, subprogram, block statement, or package. Similarly, an attribute specification for an attribute of an interface object of a design unit, subprogram, block statement, or package shall appear immediately within the declarative part of that design unit, subprogram, block statement, or package. ...

The design unit is the entity declaration (3.2 Entity declarations), a primary unit (13.1 Design units). This semantic restriction has been in place in every IEEE Std 1076 revision (-1987 through -2008, prior to -2008 found in 5.2 Attribute specification). Modelsim is wrong to 'compile' your specifications.

Xilinx's Vivado synthesis historically takes advantage of the Modelsim behavior. What's funny here is Vivado inconsistently adheres to the semantic requirement of the first quoted sentence of 7.2 above which is also found in earlier revisions but not the second. You can declare an attribute on an entity in the entity declarative part while Vivado at least historically required specify attributes on ports in the architecture declarative part.

All isn't lost when using ghdl. There's a command line argument that can be passed during analysis to relax various rules to match Modelsim's behavior where relied on by third party tools.

ghdl -a --std=08 --ieee=synopsys -frelaxed-rules --work=work vivado_rtl_island.vhdl
vivado_rtl_island.vhdl:28:33:warning: attribute for port "s_paddr" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:29:33:warning: attribute for port "s_psel" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:30:33:warning: attribute for port "s_penable" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:31:33:warning: attribute for port "s_pwrite" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:32:33:warning: attribute for port "s_pwdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:33:33:warning: attribute for port "s_pready" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:34:33:warning: attribute for port "s_prdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:35:33:warning: attribute for port "s_pslverr" must be specified in the entity [-Wspecs]

You can add the command line flag -frelaxed-rules and the errors will be converted to warnings.

The default ghdl behavior is changed for standard revision -2008. You'd note that without specifying --std=08 the default standard compliance is --std=93c which includes -frelaxed-rules and is otherwise compatible with `--std=93 (-1993). There isn't a -2008 revision with relaxed rules included.

The reason behind the semantic restriction would stem from a leading (at the time -1987) vendor not being able to implement specifying a user attribute on a port without having direct access to the port declaration. While that vendor is likely no longer providing VHDL products the restriction remains.

We find various instances of of Modelsim effectively trying to steer the standard by market share influence (they have a command line -pendanticerrors argument changing a lot of warnings to errors).

ghdl development follows their lead with the exception that strict compliance with the standard is the norm (--std=93c as a default notwithstanding) with command line arguments enabling warnings instead of errors.

The reasoning for this would be that those implementing VHDL tend to do so from the standard and not by reverse engineering the vendor with the greatest market share.

The -frelaxed-rules description may not be complete in ghdl documentation. Mention is found in the sections on VHDL standards as well as other sections.

Xilinx has been made aware of the issue. Modelsim undoubtedly knows where they vary from the standard and there currently is no vendor participation in the VHDL standard revision process.

Looking through the ghdl source tree ghdl-0.35 was released on Dec 14, 2017, and Issue 525 had a fix on Feb 7, 2018 (see src/vhdl/sem_specs.adb) to add port attributes to the architecture declarative part with -frelaxed-rules to provide the present functionality regardless of --std=08 (during the ghdl-0.36 developement cycle).

Also see Issue 838 Xilinx Vivado and Modelsim support attributes on ports differently than GHDL, on github wherein the OP sought a second opinion stating this answer is valid.

其他推荐答案

You are using VHDL2008, apparently.

With VHDL 2008, entity port attributes must go into the entity definition, i.e. you need to move your attributes before the end entity statement.

其他推荐答案

Compile like this with GHDL:

ghdl.exe -a -frelaxed-rules --std=08 --ieee=synopsys --work=work ./vivado_rtl_island.vhd

And move port attributes to Architecture block... then it will work consistently with both Xilinx Vivado and GHDL.