为什么在verilog中会发生以下重新声明错误?[英] Why does the following redeclaration error happen in verilog?

本文是小编为大家收集整理的关于为什么在verilog中会发生以下重新声明错误?的处理/解决方法,可以参考本文帮助大家快速定位并解决问题,中文翻译不准确的可切换到English标签页查看源文。

问题描述

我正在尝试实现一个简单的Verilog代码:

module test1(
    input ACLK,
     input RST,
    output test_output1,
    output test_output2
    );

//wire ACLK;
//wire RST;
reg test_output1;
reg test_output2;


assign test_output1 = ACLK;

always @(posedge ACLK or negedge RST)
begin
    if(!RST) 
    begin
        //test_output1 <=0;
        test_output2 <=0;
    end 
    else 
    begin
        //test_output1 <=0;
        test_output2 <=1;
    end
end 


endmodule

我尝试在xilinx ise中合成它时会收到以下错误消息:

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "test1.v" in library work
ERROR:HDLCompilers:27 - "test1.v" line 30 Illegal redeclaration of 'test_output1'
ERROR:HDLCompilers:27 - "test1.v" line 31 Illegal redeclaration of 'test_output2`

我无法解决此错误.任何帮助都将不胜感激.

推荐答案

如果您声明端口列表中端口的方向,则还必须声明类型.这称为ANSI样式标题.

还有一个非ANSI样式标头,可以将Portlist,定向和类型分开.如果您正在流浪IEEEEE1364-1995惯例,则必须使用非ANSI样式,并且不能声明类型(例如output reg test_output2;是非法的,而output test_output2; reg test_output2;是合法的).由于支持IEEE1364-2001 ANSI和非ANSI样式(并且非ANSI允许output reg test_output2;).所有现代的Verilog模拟器都是SystemVerilog(IEEE1800)模拟器,因此是设计师的选择. (ANSI样式更受欢迎,因为它的打字较少).

ANSI样式标头:

module test1(
  input ACLK,
  input RST,
  output test_output1,
  output reg test_output2 );

非ANSI样式标头:

module test1( ACLK, RST, test_output1, test_output2 );
  input ACLK;
  input RST;
  output test_output1;
  output test_output2;

  reg test_output2;

注意:使用IEEEE1364,您无法使用assign语句驱动reg,它必须是网络类型. IEEE1800已软化规则,它被推荐logic代替reg,但是通常,如果您要使用assign,则应该分配网络(例如wire).

.

其他推荐答案

添加以下修改:

  1. 您在分配语句中使用了test_output1,因此应该是类型的线.

    module test1(
      input wire ACLK,
      input wire RST,
      output wire test_output1, 
      output reg test_output2  
    );
    
  2. 您已经声明了test_output1和test_outpu2为输出,它是类型电线的默认值,因此您只需要根据用法隐式指定电线或reg,/p>

    // reg test_output1;
    // reg test_output2;
    

本文地址:https://www.itbaoku.cn/post/2091003.html

问题描述

I'm trying to implement a simple verilog code as below:

module test1(
    input ACLK,
     input RST,
    output test_output1,
    output test_output2
    );

//wire ACLK;
//wire RST;
reg test_output1;
reg test_output2;


assign test_output1 = ACLK;

always @(posedge ACLK or negedge RST)
begin
    if(!RST) 
    begin
        //test_output1 <=0;
        test_output2 <=0;
    end 
    else 
    begin
        //test_output1 <=0;
        test_output2 <=1;
    end
end 


endmodule

I get the following error message when I try to synthesize it in Xilinx ISE:

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "test1.v" in library work
ERROR:HDLCompilers:27 - "test1.v" line 30 Illegal redeclaration of 'test_output1'
ERROR:HDLCompilers:27 - "test1.v" line 31 Illegal redeclaration of 'test_output2`

I am unable to resolve this error. Any help would be highly appreciated.

推荐答案

If you declare the directional of the port in the portlist, you must also declare the type. This is referred to as an ANSI style header.

There is also a non-ANSI style header that separates the portlist, directional, and type. If you are fallowing IEEE1364-1995 convention then you must use non-ANSI style and you cannot declare the type (e.g. output reg test_output2; is illegal, while output test_output2; reg test_output2; is legal). Since IEEE1364-2001 ANSI and non-ANSI style is supported (and the non-ANSI allows output reg test_output2;). All modern Verilog simulators are SystemVerilog (IEEE1800) simulators, therefore it is the designers choice. (ANSI style is more popular as it is less typing).

ANSI style header:

module test1(
  input ACLK,
  input RST,
  output test_output1,
  output reg test_output2 );

Non-ANSI style header:

module test1( ACLK, RST, test_output1, test_output2 );
  input ACLK;
  input RST;
  output test_output1;
  output test_output2;

  reg test_output2;

Note: With IEEE1364, you can not drive a reg with an assign statement, it must be a net type. IEEE1800 has softened the rule the it is recommenced logic in stead of reg, but generally if you are going to use assign then you should be assigning a net (e.g. wire).

其他推荐答案

Add following modification:

  1. You used test_output1 in assign statement so it should be of type wire.

    module test1(
      input wire ACLK,
      input wire RST,
      output wire test_output1, 
      output reg test_output2  
    );
    
  2. You have already declared test_output1 and test_outpu2 as output and it is by default of type wire, so you just have to implicitly specify wire or reg according to usage,

    // reg test_output1;
    // reg test_output2;