我怎样才能在多个模块中共享和使用仅仅一个RAM模块?[英] How can I share and use just one RAM module in multiple modules?

本文是小编为大家收集整理的关于我怎样才能在多个模块中共享和使用仅仅一个RAM模块?的处理/解决方法,可以参考本文帮助大家快速定位并解决问题,中文翻译不准确的可切换到English标签页查看源文。

问题描述

我想在 RAM 中写入一个模块,然后将其读取到另一个模块中.我怎样才能做到这一点?我认为必须有一种方法可以通过引用其他模块来传递 RAM 模块.例如:

在模块 A 中:

// write in ram and pass to module B

ram ram_ins();
ram_ins.wr_en = 1;
ram_ins.addr = 1;
ram_ins.data_in = 1234;
B b_ins(ram_ins); // pass by reference the ram_ins to the module B 

在模块 B 中:

// read from ram 

ram_ins.addr = 1;
reg [7:0] a;
assign a = ram_ins.data_out

模块 B 中的寄存器 a 必须是 1234,因为在模块 A 中,1234 被写入 RAM 的地址 1.

推荐答案

您可以从需要一些控制模块或通信总线的其他模块访问 RAM.例如 Altera UFM I2C 接口.RAM可以由模块A写入和由模块B读取不同时钟(双端口RAM):

http://www.asic-world.com/examples/verilog/ram_dp_sr_sw.html

http://www.asic-world.com/examples/verilog/ram_dp_ar_aw.html

在某个抽象级别上,I2C 设备地址是您的参考.

对不起我的英语.

本文地址:https://www.itbaoku.cn/post/2091004.html

问题描述

I want to write a module in RAM and then read from the same into another module. How can I do this? I think there must be a way to pass RAM modules by referencing to other modules. For example:

In module A:

// write in ram and pass to module B

ram ram_ins();
ram_ins.wr_en = 1;
ram_ins.addr = 1;
ram_ins.data_in = 1234;
B b_ins(ram_ins); // pass by reference the ram_ins to the module B 

In module B:

// read from ram 

ram_ins.addr = 1;
reg [7:0] a;
assign a = ram_ins.data_out

Register a in module B must be 1234, because in module A 1234 is written in address 1 of RAM.

推荐答案

You can access to RAM from other modules you need some control module for this or communication bus. For example Altera UFM I2C interface. RAM can be write by module A and read by module B with different clocks (Dual-ported RAM):

http://www.asic-world.com/examples/verilog/ram_dp_sr_sw.html

http://www.asic-world.com/examples/verilog/ram_dp_ar_aw.html

At a certain level of abstraction I2C device address is your reference.

Sorry for My English.