lattice FPGA内部振荡器的模拟问题[英] lattice FPGA internal oscillator simulation issues

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问题描述

我正在尝试模拟模型上的ICE5LP1K FPGA内部振荡器.我的设计包括以下实例:

SB_HFOSC OSCInst1 (
  .CLKHFEN(1'b1),
  .CLKHFPU(1'b1),
  .CLKHF(CLKLF)
) 

我包括sb_ice_syn.v文件,但有一个设计加载错误:

错误:../testbench/sb_ice_syn.v(26066):模块'sb_hfosc_core'未定义

我无法在晶格安装文件夹中找到SB_HFOSC_CORE模块. 我在哪里可以找到错过的模块?

推荐答案

使用PLL的晶格ICE40家族(ICE5LP1K设备)设计进行模型模拟,要求包括PLL的Verilog模型.这在晶格应用程序注释an006(请参阅" C:\ lscc \ icecube2.2015.04 \ doc \ doc \ modelsim_an006.pdf"中的" C:\ lscc \ icecube2.2015.04 for Chistal IceCube2版本)":

>

如果您的设计包含PLL,请在$ inst_dir/verilog中添加abiptbs8.v和abiwtcz4.v.为了对具有PLL的VHDL设计进行同步后模拟,您将需要混合语言模拟器,因为PLL模型(Abiptbs8.v)仅以Verilog格式获得. 如果该设计包含硬化的IP原始词,请添加加密的Verilog仿真库SB_IPE_IPENC_MODELSIM.V在$ inst_dir/verilog中可用.

另一种选择是,如果您编写了SB_HFOSC_CORE pll核心的简单仿真模型,然后将其包含在模拟中,因为我假设您的重点是验证其余设计,因此您可能只需要PLL给出可用的时钟.

其他推荐答案

现在正在工作. 我在sb_ice_ipenc_modelsim.v

中找到了丢失的模块

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问题描述

I'm trying to simulate ICE5LP1K FPGA internal oscillator on ModelSim. My design includes the following instance:

SB_HFOSC OSCInst1 (
  .CLKHFEN(1'b1),
  .CLKHFPU(1'b1),
  .CLKHF(CLKLF)
) 

I included sb_ice_syn.v file but have a design loading error:

Error: ../testbench/sb_ice_syn.v(26066): Module 'SB_HFOSC_CORE' is not defined

I'm not able to find SB_HFOSC_CORE module in the lattice installation folder. Where can I find the missed modules?

推荐答案

Doing ModelSim simulation of a Lattice ICE40 family (ICE5LP1K device) design with PLLs requires that a Verilog model of the PLL is included. This is described in Lattice Application Note AN006 (see "c:\lscc\iCEcube2.2015.04\doc\Modelsim_AN006.pdf" for latest iCEcube2 version) on page 9:

If your design contains PLL, add ABIPTBS8.v and ABIWTCZ4.v in $INST_DIR/verilog. For performing Post-Synth simulation for a VHDL design having PLL, you will require a mixed-language simulator, since the PLL model (ABIPTBS8.v) is available only in verilog format. If the design contains Hardened IP primitives, add the encrypted Verilog simulation library sb_ice_ipenc_modelsim.v available in $INST_DIR/Verilog.

An alternative is if you write a simple simulation model of the SB_HFOSC_CORE PLL core, and then include this in the simulation, since I assume that your focus is on verification of the remaining design, so you probably only need the PLL to give a usable clock.

其他推荐答案

It is working now. I found the missing module in the sb_ice_ipenc_modelsim.v