Verilog:内存块实例化[英] Verilog : Memory block Instantiation

本文是小编为大家收集整理的关于Verilog:内存块实例化的处理/解决方法,可以参考本文帮助大家快速定位并解决问题,中文翻译不准确的可切换到English标签页查看源文。

问题描述

我使用以下代码在Verilog中实例化2D内存

reg  [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

reg  [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

这种实例化在模拟中起作用,但在实际合成和RTL分析完成

时无法正常工作

任何人都可以对我详细说明吗?

推荐答案

用于Altera设备: com/support/support-resources/design-examples/design-software/verilog/ver_ram.html

对于Xilinx设备(由Paebbels给出): 文档/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf (第3章,"初始化ram contents")

用于晶格设备: latticesemi.com/~/mmedia/latticesemi/documents/usermanuals/ei/icecube2_2013-08_userguide.pdf?document_id = 50165 ("初始化推断RAM")

对于微膜设备: http://www.microsemi.com/document-portal/doc_view/129865-ac162-ram-initialization-and-rom-emulation-in-proasic-sup-u- plus-u-sup-devices-app-note

与Google进行了简短的搜索,我发现了这一点: 如何初始化推断块RAM的内容)在Verilog

只是Google IT: - )

本文地址:https://www.itbaoku.cn/post/2091008.html

问题描述

I used the following code to instantiate 2-D memory in a verilog

reg  [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

reg  [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done

Can anyone elaborate to me as in how that is possible?

推荐答案

For Altera devices: https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_ram.html

For Xilinx devices (as given by Paebbels): http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf (Chapter 3, "Initializing RAM Contents")

For Lattice devices: http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/EI/iCEcube2_2013-08_userguide.pdf?document_id=50165 ("Initializing Inferred RAM")

For Microsemi devices: http://www.microsemi.com/document-portal/doc_view/129865-ac162-ram-initialization-and-rom-emulation-in-proasic-sup-u-plus-u-sup-devices-app-note

A short search with google and I found this: How to initialize contents of inferred Block RAM (BRAM) in Verilog

Just google it :-)