是否有办法在FPGA上存储百万比特的矩阵?[英] Is there a way to store a matrix of million bits on FPGA?

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问题描述

我正在努力在FPGA上实施频道解码器.相当地,问题总结为:

1)我有一个矩阵.我对行进行了一些计算.然后,我在列上进行一些计算.

解码器基本上拾取了矩阵的每一行,执行一些操作并移至下一行.它与列相同.

但是,解码器在1023 * 1023矩阵上运行,即我有1023行和1023列.

有效的小测试用例: 我首先创建了一个reg [1022:0] product_code [0:1],即2行和1023列.输出是预期的.但是,LUT利用率显示为9%.然后,我将大小增加到10行和1023列(Reg [1022:0] product_code [0:9]),也可以按预期工作.但是资源利用率已达到27%.

现在,我的目标是工作获得1023行和1023列.我什至没有合成.是否有更好的方法将此类矩阵存储在FPGA上?

我真的很感谢任何反馈!!!

推荐答案

您可以从制造商数据表中找到FPGA拥有的存储量.但是,这些记忆是高度可配置的.

因此,可以将36宽的内存用作36x1或18x2或4x9单元.您可以阅读例如36位,但将数据分为8个单位4位.分别处理每个咬合,然后再次写下整个背部.

确保您使用同步记忆,因为所有FPGA中的所有大存储器块都是同步的.如果您开始使用异步记忆,则必须从LUTS构建记忆,并且您很快就会用完.

还要提防您的行和列处理必须考虑到数据的存储方式.您可以例如存储数据行.使用nibbles作为例如:当您读取一个36内存条目时,会为您排8个nibbles.但是在列模式下,一个读取为您提供了8个相邻列的前8个条目.因此,理想情况下,您应该同时同时处理8列.

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问题描述

I am working towards the implementation of a channel decoder on an FPGA. Esentially , the problem sums up to this :

1) I have a matrix . I do some computations on the rows. Then, I do some computations on the columns.

The decoder basically picks up each row of the matrix, performs some operations and move onto the next row. It does the same with the columns.

The decoder however operates on a 1023 * 1023 matrix i.e I have 1023 rows and 1023 columns.

Small test case that works : I first created a reg [1022:0] product_code[0:1] i.e 2 rows and 1023 columns. The output is as expected. However, the LUT utilization shows up to be 9 percent approximately. Then , I increase the size to 10 rows and 1023 columns(reg [1022:0] product_code[0:9]) which works as expected too. But the resource utilization has gone up to 27 percent.

Now my goal is to work get 1023 rows and 1023 columns. I does not even synthesize. Is there a better way to store such matrix on the FPGA ?

I would really appreciate any feedback !!!

推荐答案

You can find out the amount of storage an FPGA has from the manufacturers data sheet. However those memories are highly configurable.

Thus a 36 bit wide memory can be used as 36x1 or 18x2 or 4x9 units. Alternative you can read units of e.g. 36 bits but split the data yourself in 8 units of 4 bits. Process each nibble separately and write the whole back again.

Make sure your are using synchronous memories as all big memory blocks in all FPGAs are synchronous. If you start using asynchronous memories, the memories must be build from LUTS and you run out very quickly.

Also beware that your row and column processing must take into account how the data is stored. You can e.g. store the data row-wise. Using nibbles as example: when you read one 36 memory entry, that gives you a row of 8 nibbles. But in column mode one read gives you the first 8 entries of 8 adjacent columns. So there you should ideally process 8 columns in parallel at the same time.