如何用VHDL将24MHz和12MHz时钟转换为8MHz时钟?[英] How to convert 24MHz and 12MHz clock to 8MHz clock using VHDL?

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问题描述

我正在使用VHDL编写代码,将24MHz和12 MHz时钟转换为8 MHz时钟.谁能在此编码中帮助我?提前致谢.

推荐答案

这是FPGA吗?或者是其他东西?您真的在划分时钟还是只是信号?对于三个计数器的分歧,请尝试以下链接:

divide_by_3.html

和2/3:

http://www.edaboard.com/thread42620.html

其他推荐答案

正如马丁已经说过的那样,使用Xilinx建议使用时钟管理设备,以将时钟降低到较低的速率.

虽然您可能很想使用逻辑和计数器实现时钟分隔线,但您将无法获得良好的合成结果.

这里有一些提示:

  • 一定要密切阅读并遵循有关设备的时钟管理硬件的建议.可能有很多与电力,重置,锁定时钟锁的丢失等有关的"陷阱"
  • 确保您在其规格中操作时钟管理设备.有关更多信息,请参见设备的数据表(在这种情况下为S3-A).
  • 使用FPGA编辑器验证时钟管理单元的正确放置和配置(即,它最终在芯片上的正确位置)
  • 遵守反馈时钟和时钟缓冲的建议实践.

其他推荐答案

使用DCM或PLL(取决于FPGA的家族) - 文档中有示例.如果您告诉我们哪个家庭,我也许可以更直接地指出您.

编辑: 正如您所说的Spartan 3ADSP-您需要:

  • 使用核心发电机时钟向导为您创建带有所需的组件的VHDL或Verilog文件,希望您永远不需要了解正在发生的事情
  • 阅读该芯片的USERGUIDE的图书馆指南和DCM部分,并自行实例化DCM,并将正确的通用/参数应用于它.

配置完成0后,不要忘记将重置脉冲应用于DCM,并确保脉冲持续足够长的时间.每个家庭的最小脉冲长度都不一样,我不记得那个芯片的头顶,因此请检查数据表.

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问题描述

I am writing a code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance.

推荐答案

Is this for an FPGA? Or something else? Are you really dividing a clock, or just a signal? For a divide by three counter, try this link:

http://www.asic-world.com/examples/vhdl/divide_by_3.html

And for a 2/3:

http://www.edaboard.com/thread42620.html

其他推荐答案

As Martin has already said, use a clock management device by Xilinx recommendations in order to divide your clock down to a lower rate.

While you might be tempted to implement a clock divider using logic and a counter, you will not obtain good synthesis results.

Here are some tips:

  • Be sure to closely read and follow recommendations for the clock management hardware for your device. There can be quite a few "gotchas" related to power-up, reset, loss of clock lock, etc.
  • Make sure that you are operating the clock management device within its specifications. See your device's datasheet for more information (in this case for the S3-A).
  • Use FPGA Editor to verify correct placement and configuration of your clock management units (i.e. did it end up in the right spot on the chip)
  • Adhere to recommended practices for feedback clocks, and clock buffering.

其他推荐答案

Use a DCM or PLL (depending on the family of FPGA) - there's examples in the documentation. If you tell us which family, I might be able to point you more directly.

EDIT: As you say Spartan 3ADSP - you need to either:

  • Use the Core Generator Clocking Wizard to create you a VHDL or Verilog file with the components you need in and hope you never need to understand what's going on
  • Read the libraries guide and the DCM section of the Userguide for that chip and instantiate a DCM on your own and apply the correct generics/parameters to it.

Don't forget to apply a reset pulse to the DCM after configuration has finished 0 and make sure that pulse lasts long enough. The min pulse length is different for each family, I don't recall off the top of my head what it is for that chip, so check the datasheet.