VHDL相当于Verilog @(posedge clk)[英] VHDL equivalent for Verilog @(posedge clk)

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问题描述

我不熟悉Verilog.我尽力将其转换.

在模拟时钟时从" 0"到'x',这很奇怪. 我怀疑这部分是问题

repeat(9) @(posedge clk);
   DataIn_i <= 1'b1;
   DataIn_q <= 1'b1;
@(posedge clk);
  FillSel <= 1'b0;
  DataIn_i <= 1'b0;
  DataIn_q <= 1'b0;

这是两个长椅的链接.

verilog板凳 - http://a.pomf.se/fvamqd.v VHDL板凳 - http://a.pomf.se/riolvf.vhd

欢迎任何输入,谢谢.

编辑:任何人都可以解释上面给出的Verilog代码吗?

推荐答案

将Verilog的@posedge clk)转换为VHDL取决于其位于始终或初始块中的位置.如果这是块的第一个结构,您可以做

Verilog:

always @(posedge signal)
begin
...
end

vhdl:

process(signal)
begin
  if rising_edge(signal) then  -- Older VHDL if (signal'event and signal = '1')
  ...
  end if;
end process;

嵌入在块中时,使用wait until语句:

Verilog: @(posedge clk);
VHDL:    wait until rising_edge(signal);

Verilog:  forever ...
VHDL:     loop ... end loop

Verilog: repeat(n) ...
VHDL:    for i in 1 to n loop ... end loop;

请注意,当我为verilog编写时,那是针对以下的单个语句或以下单个开始/结束块.

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问题描述

I am not familiar with verilog. I did my best trying to convert it.

While simulating the clock is going from '0' to 'x' which is weird. I am suspecting this part to be the problem

repeat(9) @(posedge clk);
   DataIn_i <= 1'b1;
   DataIn_q <= 1'b1;
@(posedge clk);
  FillSel <= 1'b0;
  DataIn_i <= 1'b0;
  DataIn_q <= 1'b0;

here are links to both benches.

Verilog bench - http://a.pomf.se/fvamqd.v Vhdl bench - http://a.pomf.se/riolvf.vhd

any input is welcome,thanks in advance.

EDIT: Can anyone please explain the verilog code given above?

推荐答案

Translating Verilog's @posedge clk) to VHDL depends on where it is located in an always or initial block. If it's the very first construct of the block, you can do

Verilog:

always @(posedge signal)
begin
...
end

VHDL:

process(signal)
begin
  if rising_edge(signal) then  -- Older VHDL if (signal'event and signal = '1')
  ...
  end if;
end process;

When embedded in the block, use the wait until statement:

Verilog: @(posedge clk);
VHDL:    wait until rising_edge(signal);

Verilog:  forever ...
VHDL:     loop ... end loop

Verilog: repeat(n) ...
VHDL:    for i in 1 to n loop ... end loop;

Note that when I write ... for Verilog, that is for the single statement that follows, or a single begin/end block that follows.