在Verilog合成中,如何在for循环中用二进制比较整数值来生成延迟?[英] How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

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问题描述

你好朋友,我仍然不知道如何生成verilog的延迟进行合成,并将其称为verilog中的任何行以进行合成...为了找到此信息,我写了一个代码,但是如果您知道如何生成延迟,请帮助我并打电话到任何行c函数*……实际上是朋友,如果您告诉我为什么我在这里使用循环,那么我的答案是 - 我想将指针移入内部循环直到和除非他们完成了我为延迟生成的计算 ..

module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;


always
begin
#50 Clk=~Clk;
end

 always @(posedge Clk)
     begin
      a=1'b1;
      delay();
      a=1'b0;
      delay();
       a=1'b1;
      end 


  task delay();
   begin
   for(i=0;i==(stmp==4'b1111);i=i+1)
  begin
   @(posedge Clk)
    begin
    stmp=stmp+1;
    end
    end

  if(stmp==4'b1111)
  begin
  stmp=4'b0000;   
  end    

  end
  endtask


    endmodule 

实际上我想要这个 a = 1'b0;延迟(); a = 1'b1; 请帮助我已经尝试使用以前使用计数器延迟生成,但对我不起作用.....如果您使用 Counter 知道相同的话,请告诉我.. ....谢谢

推荐答案

// will generate a delay of pow(2,WIDTH) clock cycles 
// between each change in the value of "a"
`define WIDTH 20

reg [`WIDTH:0] counter;
wire a = counter[`WIDTH];

always @(posedge Clk)
  counter <= counter + 1;

您必须根据a的更改和Clk信号的速率

之间的延迟选择适合WIDTH> WIDTH

其他推荐答案

这个问题是如何使用计数器进行合成和内部呼叫始终阻止的verilog延迟? .

我发现有一部分代码很麻烦:

always @(posedge Clk) begin
  a = 1'b1;
  delay() ;
  a = 1'b0;
end 

nb:一个很好的规则是始终在边缘触发过程中使用<=.

现在让我们考虑延迟();作为#10ns;的任务我们使用当前代码所获得的任务是:

time  0ns a = x;
time  1ns a = 1; //Posedge of clk
time  6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed

使用<=,我认为您应该看到类似的行为.但是,当涉及诸如#1ns之类的综合延迟时

always @(posedge Clk) begin
  a <= 1'b0;
end

使用硬件说明语言一种好方法是考虑我们要暗示的硬件并用语言描述.构造always @(posedge Clk)用于暗示触发器,即每个时钟周期的输出一次变化.在问题中,我们有3次更改值3次,从1个时钟边缘我不知道您要暗示什么硬件.

您无法提供内联综合延迟​​.为了使always @(posedge clk)块可合成,它们应该能够在零时间内执行.您需要引入状态机,以在时钟边缘之间保持状态.我想我已经提供了一个很好的示例,说明了如何在我以前的答案中.如果要编程的延迟,请参见 mcleod_ideafix的答案.

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问题描述

Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function*......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation..

module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;


always
begin
#50 Clk=~Clk;
end

 always @(posedge Clk)
     begin
      a=1'b1;
      delay();
      a=1'b0;
      delay();
       a=1'b1;
      end 


  task delay();
   begin
   for(i=0;i==(stmp==4'b1111);i=i+1)
  begin
   @(posedge Clk)
    begin
    stmp=stmp+1;
    end
    end

  if(stmp==4'b1111)
  begin
  stmp=4'b0000;   
  end    

  end
  endtask


    endmodule 

Actually friends I want this a=1'b0; delay(); a=1'b1; please help I already tried delay Generation Using Counter previously but it not works for me.....If you know same using Counter then please tell me......Thanks

推荐答案

// will generate a delay of pow(2,WIDTH) clock cycles 
// between each change in the value of "a"
`define WIDTH 20

reg [`WIDTH:0] counter;
wire a = counter[`WIDTH];

always @(posedge Clk)
  counter <= counter + 1;

You have to choose a suitable value for WIDTH according to how much delay you want between changes in a and the rate of your Clk signal

其他推荐答案

This question is a more succinct version of How to generate delay in verilog using Counter for Synthesis and call inside Always block?.

There is one section of code that I find troublesome:

always @(posedge Clk) begin
  a = 1'b1;
  delay() ;
  a = 1'b0;
end 

NB: A good rule to stick to is to always use <= in edge triggered processes.

for now lets think of the delay(); task as #10ns; What we get with the current code would be:

time  0ns a = x;
time  1ns a = 1; //Posedge of clk
time  6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed

Using <= and I think you should see a similar behaviour. However when it comes to synthesis delays like #1ns can not be created and the whole thing will collapse back down to :

always @(posedge Clk) begin
  a <= 1'b0;
end

With a hardware description language a good approach is to consider what hardware we want to imply and describe it in the language. The construct always @(posedge Clk) is used to imply flip-flops, that is the output changes once per clock cycle. In the question we have a changing value 3 times, from 1 clock edge I do not know what hardware you are trying to imply.

You can not provide an inline synthesizable delay. For always @(posedge clk) blocks to be synthesizable they should be able to execute in zero time. You need to introduce a state machine to keep state between clock edges. I think I have already provided a good example on how to do this in my previous answer. If the delay is to be programmable then see mcleod_ideafix's answer.