# 在Verilog合成中，如何在for循环中用二进制比较整数值来生成延迟？[英] How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

### 问题描述

```module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;

always
begin
#50 Clk=~Clk;
end

always @(posedge Clk)
begin
a=1'b1;
delay();
a=1'b0;
delay();
a=1'b1;
end

begin
for(i=0;i==(stmp==4'b1111);i=i+1)
begin
@(posedge Clk)
begin
stmp=stmp+1;
end
end

if(stmp==4'b1111)
begin
stmp=4'b0000;
end

end

endmodule
```

## 推荐答案

```// will generate a delay of pow(2,WIDTH) clock cycles
// between each change in the value of "a"
`define WIDTH 20

reg [`WIDTH:0] counter;
wire a = counter[`WIDTH];

always @(posedge Clk)
counter <= counter + 1;
```

## 其他推荐答案

```always @(posedge Clk) begin
a = 1'b1;
delay() ;
a = 1'b0;
end
```

nb:一个很好的规则是始终在边缘触发过程中使用<=.

```time  0ns a = x;
time  1ns a = 1; //Posedge of clk
time  6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed
```

```always @(posedge Clk) begin
a <= 1'b0;
end
```

### 问题描述

Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function*......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation..

```module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;

always
begin
#50 Clk=~Clk;
end

always @(posedge Clk)
begin
a=1'b1;
delay();
a=1'b0;
delay();
a=1'b1;
end

begin
for(i=0;i==(stmp==4'b1111);i=i+1)
begin
@(posedge Clk)
begin
stmp=stmp+1;
end
end

if(stmp==4'b1111)
begin
stmp=4'b0000;
end

end

endmodule
```

Actually friends I want this a=1'b0; delay(); a=1'b1; please help I already tried delay Generation Using Counter previously but it not works for me.....If you know same using Counter then please tell me......Thanks

## 推荐答案

```// will generate a delay of pow(2,WIDTH) clock cycles
// between each change in the value of "a"
`define WIDTH 20

reg [`WIDTH:0] counter;
wire a = counter[`WIDTH];

always @(posedge Clk)
counter <= counter + 1;
```

You have to choose a suitable value for WIDTH according to how much delay you want between changes in a and the rate of your Clk signal

## 其他推荐答案

This question is a more succinct version of How to generate delay in verilog using Counter for Synthesis and call inside Always block?.

There is one section of code that I find troublesome:

```always @(posedge Clk) begin
a = 1'b1;
delay() ;
a = 1'b0;
end
```

NB: A good rule to stick to is to always use <= in edge triggered processes.

for now lets think of the delay(); task as #10ns; What we get with the current code would be:

```time  0ns a = x;
time  1ns a = 1; //Posedge of clk
time  6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed
```

Using <= and I think you should see a similar behaviour. However when it comes to synthesis delays like #1ns can not be created and the whole thing will collapse back down to :

```always @(posedge Clk) begin
a <= 1'b0;
end
```

With a hardware description language a good approach is to consider what hardware we want to imply and describe it in the language. The construct always @(posedge Clk) is used to imply flip-flops, that is the output changes once per clock cycle. In the question we have a changing value 3 times, from 1 clock edge I do not know what hardware you are trying to imply.

You can not provide an inline synthesizable delay. For always @(posedge clk) blocks to be synthesizable they should be able to execute in zero time. You need to introduce a state machine to keep state between clock edges. I think I have already provided a good example on how to do this in my previous answer. If the delay is to be programmable then see mcleod_ideafix's answer.